Technical Field
The present invention relates to a valid data merging method for a non-volatile memory module and a memory controller and a memory storage apparatus using the same.
Description of Related Art
The growth of digital cameras, mobile phones, and MP3 players has been rapid in recent years. Consequently, the consumers' demand for storage media has increased tremendously. A rewritable non-volatile memory is one of the most adaptable memories for portable electronic products such as laptop computer due to its data non-volatility, low power consumption, small volume, non-mechanical structure and high read/write speed. A solid state drive (SSD) is a memory storage apparatus which utilizes a flash memory as its storage medium. For these reasons, the flash memory has become an import part of the electronic industries.
A flash memory storage module includes a plurality of physical erasing units, and each of the physical erasing units has a plurality of physical programming units, and a data is written into the physical erasing unit according to a sequence of the physical programming units. In addition, the physical programming units already written with data must be erased before it can be used again for writing data. In particular, the physical erasing unit is served as a smallest unit for erasing, whereas the physical programming unit is served as a smallest unit for programming (or writing). Therefore, in a management of the flash memory module, the physical erasing units may be divided into a data area and a spare area.
The physical erasing units of the data area are configured to store data stored by a host system. More specifically, a memory management circuit in the memory storage apparatus converts logical access addresses to be accessed by the host system into logical pages of logical blocks, and maps the logical pages of the logical blocks to the physical programming units of the physical erasing units of the data area. Namely, in the management of the flash memory module, the physical erasing units of the data area are regarded as the physical erasing units already being used (e.g., already stored with data written by the host system). For example, the memory management circuit uses a logical address-physical address mapping table for recording mapping relations between the logical pages and the physical programming units in the data area.
The physical erasing units of the spare area are used to alternatively replace the physical erasing units in the data area. More specifically, as described above, the physical erasing units written with data must be erased before it can be used again for writing data. Therefore, the physical erasing units of the spare area are designed to replace the physical erasing units mapped to the logical blocks for writing update data. Accordingly, the physical erasing units in the spare area are empty or the physical erasing units that can be used for writing data.
In a common writing operation, after the data is written into the physical erasing units in the spare area, the memory management circuit in the memory storage apparatus does not immediately change the mapping relations between the logical pages and the physical programming units in the logical address-physical address mapping table, but stores mapping information corresponding to the writing operation by using a physical address-logical address mapping table stored in a buffer memory. Specifically, in the writing operation, the memory management circuit writes the update data into one physical erasing unit (also known as an active physical erasing unit) in the spare area, and records the mapping information between the logical pages related to such writing operation and the physical programming units for storing the update data into the physical address-logical address mapping table. Only at the appropriate time (e.g., when the host system is in an idle time or the physical address-logical address mapping table is fully written), the memory management circuit loads the corresponding logical address-physical address mapping table according to the mapping information in the physical address-logical address mapping table in order to update the mapping information between the logical pages and the physical programming units.
Further, when the number of spare physical erasing units in the spare area is not greater than a predefined value, the memory management circuit will perform a valid data merging procedure. Specifically, when the number of the spare physical erasing units in the predefined value is not greater than the predefined value, it indicates that the number the physical erasing units in the spare area is insufficient for writing. As such, the memory management circuit performs a data merging procedure also by loading the logical address-physical address mapping table in order to release more space for the spare area.
Because a storage space of the physical address-logical address mapping table is usually corresponding to one or multiples of the size of the active physical erasing unit in the spare area selected for writing the update data, when the physical address-logical address mapping table is fully written, a situation where the active physical erasing unit is fully written by the update data of the writing operation may often occur accordingly. When the active physical erasing unit is fully written by the update data and the number of the spare physical erasing units in the spare area is not greater than the predefined value, the memory management circuit will perform aforesaid valid data merging procedure. In other words, before the valid data merging procedure is performed, an erasing operation for the physical address-logical address mapping table is usually performed to update the logical address-physical address mapping table. Because the valid data merging procedure and the erasing operation are two mechanisms independent from each other in conventional art, in the case where the two mechanisms both require to load the logical address-physical address mapping table into the buffer memory, the same logical address-physical address mapping table may be repeatedly loaded into the buffer memory, such that a response-waiting time of the host system may become excessively long.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.